1. Field of the Invention
The present invention relates generally to the field of semiconductor devices, and more particularly to a method for fabricating semiconductor device with relatively low contact resistance.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of field effect transistors (FETs), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace conventional planar field effect transistors.
In current techniques, in order to meet the sub-lithographic features, semiconductor device manufacturers often utilize sidewall image transfer (SIT) technology to form required fin structures. In general, SIT may include the following steps. First, a plurality of dummy patterns is formed on a substrate. Then, spacers are respectively formed on each sidewall of the dummy patterns through a deposition and an etching process. Subsequently, patterns of the spacers may be transferred to the substrate by using the spacers as mask. In this way, a plurality of paralleled fin structures may be formed in the substrate and the physical dimensions of these fin structures may be used to define the shape and the width of the carrier channel in the transistors. However, the small surface area of these fin structures often limits the size of the contact area between itself and the corresponding electrical contact structure. Since the contact resistance is inversely proportional to the contact area, apparent voltage drop often occurs inevitably on the interface between the fin structures and the electrical contact structures within the well pick-up region, which is definitely bad for the electrical performance of the transistors.
In order to overcome the above-mentioned high contact resistance within the well pick-up region, there is a need to provide a modified semiconductor device and a fabrication method thereof.